This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-088962, filed Mar. 28, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a gate array having interchangeability with programmable devices (hereafter referred to as xe2x80x9cFPGAxe2x80x9d) such as FPGAs (Field Programmable Gate Array) and PLDs (Programmable Logic Device).
Logic LSIs are divided, from the view of users, that is, according to the customizing grade, into standard logic LSIs, semi-custom LSIs and full-custom LSIs. Generally a standard LSI is one of which specifications are fixed between users, a full-custom LSI is one of which specifications are specific to each user, and a semi-custom LSI is one of which manufacturing processes are halfway common and of which subsequent manufacturing processes are specific to each user.
Moreover, logic LSIs are divided, according to their use, into general LSIs and specific LSIs. A specific LSI is called ASIC (Application Specific IC) and includes, for example, ASSPs (Application Specific Standard products) and ASCPs (Application Specific Custom products).
As a representative example of the ASIC a gate array is known. The gate array is a kind of semi-custom LSI and has advantages of the shortest development period among the ASCIs and low cost. In the gate array, as is well-known, a wafer having a transistor array (Diffused Wafer, hereafter referred to as DW) are formed in advance by using a common mask for a plurality of product types, and subsequently, by using this wafer and different wiring masks for various product types, LSIs having different functions can be realized.
On the other hand, in recent years, a FPGA is widely noticed as a logic LSI different from the ASIC. The FPEG is already completed as a chip, however, it doesn""t operate as it is, and it is characterized in that a user can program data into a memory in the FPGA to realize a LSI (product) having desired functions. And in comparison to the ASICs such as gate arrays the FPGA has advantages of a very short period from design to completion of a product, free redesign and flexibly changeable specifications.
1. INTERCHANGEABILITY
In comparison to gate arrays realizing desired functions by means of a wiring process using wiring masks after design, the FPGA permits processes from design to completion of a product to be carried out for a short period.
On the other hand, the FPGA has a disadvantage of the unit price of a chip being very high (several times to several ten times of that of a gate array). Therefore, conventionally it is typical to reduce initial costs in a trial production stage by using a FPGA in which the period from design to completion of a product is very short and to reduce mass production costs in a mass production stage by using a gate array in which the unit price of a chip is low.
Now, recent progress in FPGA technology is remarkable, an increase in gate scale and an improvement in processing speed is being realized, and further, according to the demand of the market, a FPGA capable of selecting (or changing) the type of input/output buffers is beginning to be proposed.
As shown in FIG. 1, in a FPGA provided with input/output buffers having selectivity (diversity), a standard input/output circuit block (hereafter referred to as a standard I/O cell) 12 and a special input/output circuit block (hereafter referred to as a special I/O cell) 13 are disposed, for example, on the peripheral portion of a chip 11-1.
And almost every kind of input/output buffer (usual input/output buffer) can be realized by changing the functions of the buffer in the standard I/O cell 12 by means of a program. On the other hand, for example, in an input/output buffer of LVDS (Low Voltage Differential Signal) type, the specifications thereof are strictly specified, and the standard I/O cell 12 cannot deal with this buffer. Therefore, the input/output buffer of LVDS type is fixed in structure, size and layout and is realized by means of a buffer of which functions cannot be changed by means of a program, that is, by means of the special I/O cell 13.
Now, the gate array is formed by using a DW of which substrate process (transistor forming process) has already ended and further by carrying out a wiring process by means of a wiring mask specific to each product. Therefore, basically, an input/output buffer of LVDS type can be also realized by changing a wiring mask.
However, the gate array uses a transistor of given structure and size and realizes a desired logic LSI by changing the layout of metallic wiring freely. Therefore, it is very difficult to realize a buffer having substantially the same characteristics as the input/output buffer of LVDS type in the FPGA tip.
Accordingly, as a result thereof, in a FPGA having a special I/O cell 13 as described above, it is impossible to replace a FDPA used in the development stage with a gate array in the mass production stage.
That is, conventionally, in developing a logic LSI having a special input/output buffer of which characteristics are strictly specified or a system thereof, there are no other methods than to use a FPGA both in the development stage and in the mass production stage or to replace a FPGA used in the development stage with a full-custom LSI (such as standard cell and embedded array) using a specific wiring mask in the substrate process and the wiring process in the mass production stage.
Therefore, in the former method the mass production cost is very high, and in the latter method there are problems that the period from design to mass production of a full-custom LSI is long and that the development cost is also high.
2. TEST CIRCUIT FOR EASY TEST
Conventionally, in the gate array, tests on the part of the manufacturers are very complicated and difficult due to the complicated functions of a logic LSI. Therefore, the test time for shipping inspection carried out before shipping products becomes long and the production cost is also increasing. Thus, the manufacturers think that it is preferable to load a test circuit for an easy shipping inspection in the chip in order to shorten the test time.
However, since the problems Nos. 1 to 3 as describe below are caused by loading a test circuit for an easy test in the chip, many manufactures don""t wish to load such a test circuit in the chip.
No. 1: chip size gets larger
That is, a test circuit for an easy test mounted in the chip makes the chip size larger.
No. 2: processing speed gets lower
That is, a gate circuit for changing over signals inserted between the input/output circuit and the logic circuit makes the processing speed lower.
No. 3: unnecessary external terminals (pins) get added
A test terminal (external terminal) is required for instructing the operation of the test circuit from outside of the chip, however, this test terminal is not used in normal operation.
Concerning the problem of No. 1, as a recent tendency, the gate scale becomes larger and the area of the test circuit is sufficiently small in comparison to the area of the gate array. Therefore, the area of the test circuit has only a small influence on the increase in chip size, and this problem is now not so important.
Moreover, concerning the problem of No. 2, the influence of the test circuit becomes smaller together with an enlarged and complicated gate scale, and also this problem is now not so important.
In contrast thereto, the problem of No. 3 arises independently of the gate scale, and no effective solutions have been found yet.
That is, the test terminal for shipping inspection is used only for test, and in mounting onto the print circuit substrate, there is only a bad influence that the portions to be soldered increase, thereby making the work complicated. Moreover, there arise problems that the size of a package becomes larger and that there is a possibility of causing soldering troubles in mounting due to the increasing number of the external terminals of the package.
Moreover, it is typical that each manufacturer uses a differently composed test circuit. Therefore, when a user ordered the same gate array product to two different manufacturers, the gate array products shipped from the manufacturers may have different appearances (due to an unnecessary test terminal or the like), what causes a serious hindrance when the user uses these products.
From such reasons, in the gate array, it has been decided after consulting with the user, whether a test circuit for an easy test should be loaded in the chip or not. However, users have usually a tendency of not preferring such a test circuit from the reasons as described above and, therefore, in nearly every case no test circuit for an easy test is loaded in the chip in the current condition of the gate array.
However, the test terminal makes a major contribution to the rationalization on the part of the manufacturers because it can realize an automated design in designing the test circuit and can standardize test devices used for shipping inspection on the part of the manufacturers if it can be specified to a specific terminal (specific pin) of the package of a LSI.
Therefore, the manufactures are looking forward to realize a technique permitting the test circuit for an easy test to be loaded without imposing a burden upon users.
The object of the present invention is, therefore, firstly to propose a gate array having a perfect interchangeability with a FPGA and secondly to load a test circuit for an easy test in the chip without causing demerits to users by using the gate array having interchangeability with the EPGA.
The interchangeable FPGA-GATE ARRAY is provided with a first external terminals disposed at the same positions of second external terminals of a FPGA and a gate array chip having a test circuit, and a position of a terminal for controlling the test circuit among the first external terminals is the same as a position of a data program terminal of the FPGA among the second external terminals.
The method of producing the interchangeable FPGA-GATE ARRAY according to the present invention is applied to a case in which a system is developed by using a FPGA and the system is mass-produced by using a gate array, and it comprises a series of steps of forming a logic LSI in a FPGA chip by using a data program terminal of the package of the FPGA, of forming the logic LSI and a test circuit in a gate array chip by using a wiring mask, of containing the gate array chip in which the logic LSI and the test circuit are formed in the package of the FPGA, and of using the data program terminal of the package of the FPGA as a test terminal for controlling the test circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.